#ifndef ARM_CM3_H
#define ARM_CM3_H
#include "dap_access.h"
#define DebugDCRSR               (0xE000EDF4u)//调试内核寄存器选择者寄存器
#define DebugDCRDR               (0xE000EDF8u)//调试内核寄存器数据寄存器
#define DebugDHCSR               (0xE000EDF0u)//调试停机控制及状态寄存器 DHCSR
#define DebugDHCSR_WriteKey      (0xA05F0000u)//写DHCSR KEY
#define DebugDEMCR               (0xE000EDFCu)//调试乃及监视器控制寄存器 DEMCR
#define DebugAIRCR               (0xE000ED0Cu)//应用程序中断及复位控制寄存器 写 1 << 2 reset mcu
#define DebugAIRCR_Writekey      (0x05FA0000u)//写AIRCR KEY

#define CM3_R0              (0u)
#define CM3_R1              (1u)
#define CM3_R2              (2u)
#define CM3_R3              (3u)
#define CM3_R4              (4u)
#define CM3_R5              (5u)
#define CM3_R6              (6u)
#define CM3_R7              (7u)
#define CM3_R8              (8u)
#define CM3_R9              (9u)
#define CM3_R10             (10u)
#define CM3_R11             (11u)
#define CM3_R12             (12u)
#define CM3_R13             (13u)
#define CM3_R14             (14u)
#define CM3_R15             (15u)
#define CM3_xPSR            (16u)
#define CM3_MSP             (17u)
#define CM3_PSP             (18u)
//[31:24]: CONTROL
//[23:16]: FAULTMASK
//[15:8]: BASEPRI
//[7:0]: PRIMASK
#define CM3_Special         (20u)
#define CM3_reg_w               (1 << 16)//1=写寄存器 0=读寄存器

//------this is DHCSR bit mask-------
#define S_RESET_ST          (1 << 25)//内核已经或即将复位，读后清零 DHCSR
#define S_RETIRE_ST         (1 << 24)//在上次读取以后指令已执行完成，读后清零 DHCSR
#define S_LOCKUP            (1 << 19)//1=内核进入锁定状态 DHCSR
#define S_SLEEP             (1 << 18)//1=内核睡眠中 DHCSR
#define S_HALT              (1 << 17)//1=内核已停机 DHCSR
#define S_REGRDY            (1 << 16)//1=寄存器的访问已经完成 DHCSR
//------this bit don't be affect by system reset----
#define C_SNAPSTALL         (1 << 5) //打断一个 stalled 存储器访问 DHCSR
#define C_MASKINTS          (1 << 3) //调试期间关中断，只有在停机后方可设置 DHCSR
#define C_STEP              (1 << 2) //让处理器单步执行，在 C_DEBUGEN=1 时有效 DHCSR
#define C_HALT              (1 << 1) //喊停处理器，在 C_DEBUGEN=1 时有效 DHCSR
#define C_DEBUGEN           (1 << 0) //使能停机模式的调试 DHCSR

//------this is halt debug bit mask-------
//------this bit don't be affect by system reset----
#define VC_HARDERR          (1 << 10)//发生硬 fault 时停机调试 DEMCR
#define VC_INTERR           (1 << 9) //指令/异常服务错误时停机调试 DEMCR
#define VC_BUSERR           (1 << 8) //发生总线 fault 时停机调试 DEMCR
#define VC_STATERR          (1 << 7) //发生用法 fault 时停机调试 DEMCR
#define VC_CHKERR           (1 << 6) //发生用法 fault 使能的检查错误时停机调试（如未对齐，除数为零）DEMCR
#define VC_NOCPERR          (1 << 5) //发生用法 fault 之无处理器错误时停机调试 DEMCR
#define VC_MMERR            (1 << 4) //发生存储器管理 fault 时停机调试 DEMCR
#define VC_CORERESET        (1 << 0) //发生内核复位时停机调试 DEMCR
unsigned int haltdebug(void);
unsigned int HaltCPU(void);
unsigned int StepiCPU(void);
unsigned int ResumeCPU(void);
void DebugInit(void);
unsigned int CPU_RegRead(unsigned int RegNumber,unsigned int *value);
unsigned int CPU_RegWrite(unsigned int RegNumber,unsigned int value);
unsigned int InsertBreakpointOrWatchpoint(unsigned int type,unsigned int addr,unsigned int len);
unsigned int RemovetBreakpointOrWatchpoint(unsigned int type,unsigned int addr,unsigned int len);
unsigned int IsHalted(unsigned int *stat);
unsigned int MemoryRead(unsigned int addr,unsigned char*buf,unsigned int len);
unsigned int MemoryWrite(unsigned int addr,unsigned char*buf,unsigned int len);
unsigned int TargetRunCode(unsigned int reg[]);
unsigned int WaitRAMCodeFinish(unsigned int Sec);
unsigned int GetRAMCodeReturn(unsigned int *res);
#endif